1. Technical Field
The present invention relates to integrated circuits in general, and in particular to a method and apparatus for reducing bipolar current effects in integrated circuits. Still more particularly, the present invention relates to a method and apparatus for reducing bipolar current effects in Silicon-On-Insulator (SOI) dynamic logic integrated circuits.
2. Description of the Prior Art
Among integrated circuit design families, dynamic logic circuits offer significant advantages over their static logic circuit counterparts, particularly in performance and chip area requirements. Therefore, it is desirable to use dynamic logic circuits to implement as much of the logic function of an integrated circuit design as possible. Generally speaking, dynamic logic circuits use a stored charge to represent a logic state. In operation, the charge is usually stored at a storage node during a precharge phase, and the charge is then conditionally discharged during an evaluation phase.
In recent years, the predominant processing technology for fabricating integrated circuits has been the Complementary-Metal-Oxide Silicon (CMOS) technology using silicon substrates. Although CMOS technology offers various advantages, such as low power consumption and stability, over other types of processing technologies, there are also several drawbacks associated with CMOS circuits, such as relatively slow speed and potential latch-up problems. In light of such, a new processing technology called Silicon-On-Insulator (SOI) technology has emerged. Instead of using an electrically conducting substrate like the CMOS technology, SOI utilizes an insulating substrate. A detailed description of the SOI technology can be found in Weste and Eshraghian, Principles of CMOS VLSI Design: A Systems Perspective, 2nd ed., pp. 125-130, Addison Wesley (1995), the pertinent portion of which is incorporated herein by reference.
With an insulating substrate, SOI technology provides tremendous improvements in certain circuit characteristics, such as speed and latch-up, over CMOS technology. However, when dynamic logic circuits are fabricated using SOI technology instead of the CMOS counterpart, a problem known as bipolar current effect becomes more dominant. In fact, bipolar current effect arising from SOI technology is considered a more series problem than the charge sharing problem attributed to CMOS technology. Therefore, it is desirable to provide a method and apparatus for reducing bipolar current effects in dynamic logic circuits that are fabricated using SOI technology.
In accordance with a preferred embodiment of the present invention, a dynamic logic circuit capable of reducing bipolar current effects includes a precharge transistor (or a discharge transistor), a pass transistor, a functional logic circuit block, and an inverter. Connected in series with the precharge transistor, the functional logic circuit block, which includes multiple transistors, receives signal inputs. The pass transistor, connected in parallel with the precharge transistor, receives an identical input as one of the many transistors within the functional logic circuit block. The inverter, connected to a node between the precharge transistor and the functional logic circuit block, provides an output for the dynamic logic circuit.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.